Design-Reuse

Multiprocessing speeds IC physical verification

As manufacturing processes transition to more advanced technologies at 90nm and below, design signoff requirements become increasingly more rigorous and time-consuming. With each step to more advanced ...
EDN

Interoperable DRC/LVS language standard accelerates physical verification turnaround time for advanced nodes

As Moore’s Law drives semiconductor manufacturers to deliver a consistent doubling of transistor counts every two years, the number of rules in the DRM (design rule manual) for advanced processes has ...
Electronic Design

In Verification, Physics Intrudes Forcefully At 28 nm

Getting physical The number of physical design rules has increased significantly since the 65-nm node. At 40 nm, foundry runsets totaled fewer than 1000 rules to be checked. At 28 nm, the number of ...
AOL

Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC's CoWoS™ Referenc

WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corp. (NAS: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC's new ...
Semiconductor Engineering

Physical Verification In The Cloud

Cloud computing is no longer “the next big thing”; it has become a mainstream tool for business across many industries. Our own industry of IC Design and EDA, however, has been watching the cloud ...
Semiconductor Engineering

The Route To Faster Physical Verification And Better Designs

As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to ...
EDN

SMIC Certifies Synopsys IC Validator for Signoff Physical Verification

Fully qualified 28-nm signoff physical verification runsets are available from SMIC for DRC, LVS and metal fill Certified runsets enable SMIC and Synopsys' mutual customers to leverage IC Validator In ...
Design-Reuse

UMC Certifies Synopsys IC Validator Physical Verification Tool for 28 nm

MOUNTAIN VIEW, Calif. and HSINCHU, Taiwan, April 23, 2014 – Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic ...
Electronic Design

11 Myths About Hardware-Assisted Verification

Verification expert Dr. Lauro Rizzatti debunks the myths surrounding the two tool classes of HAV platforms—hardware emulators and FPGA prototypes. What are hardware emulators and FPGA prototypes? Who ...
Business Wire

Mentor Graphics Provides Design, Verification, Thermal and Test Solutions for TSMC’s CoWoS™ Reference Flow

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corp. (NASDAQ: MENT) today announced IC physical design, verification, thermal analysis and test design tools that have been selected for TSMC’s new ...