Since DAC 2005, there has been extensive discussion about using Statistical Static Timing Analysis (SSTA) to verify current and future generations of designs manufactured at 90 nm or below. Given the ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...