Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...

As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...

Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is ...

With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis ...

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).

As today’s designs become more complex, so too do their constraints. Design functionality typically gets a lot of attention – through code review, functional verification, etc. However, the ...